1) Field of the Invention
This invention relates generally to Electro Static Discharge (ESD) devices and methods thereof and more particularly to an electrostatic discharge method and device comprising a parasitic bipolar transistor and a deep well.
2) Description of the Prior Art
In the semiconductor industry, the use of electrostatic discharge protection (ESD) devices is known. ESD circuits ensure that integrated semiconductor devices are not destroyed by static electricity during routine post-manufacture processes. However, current and foreseeable trends in the semiconductor industry are adversely impacting the effectiveness of known ESD circuits.
Designing ESD protection structures for high-speed analog and RF application is a challenge due to stringent requirement of input impedance and area. Various techniques have been invented for extending the traditional ESD protection device in RF area. Most involve some form of diode protection as diodes are very robust in carrying ESD current in forward bias. The diode solution works fine except for the series resistance which results in voltage drop in the forward conduction mode. In addition, current density of forward biased diode is limited by the current crowding of the junction. Typically reported values are in the range of 10–30 mA/um-square. If a polysilicon bounded diode is used the maximum current before destructive breakdown is limited by the local breakdown of gate oxide which is weakened by the thermal heating in the diode during ESD current conduction. Thus, maximum possible current density is sometimes never reached in polysilicon bounded diode. Simple salicide-blocked polysilicon diode is sometime used for RF ESD protection but the issue is high standby leakage through polysilicon grain boundaries. Also poly pre-dope has to be blocked in the diode area to be able to form P+/N+ junction.
The more relevant patents are US 2002/0122280A1(Ker et al.) shows a SCR device with deep-n-well structure for ESD.
U.S. Pat. No. 6,617,650b1 (Chen et al.) shows a ESD device with a buried n-well.
U.S. Pat. No. 5,903,419 (Smith) show an ESD circuit with a string of diodes.
U.S. Pat. No. 6,621,133B1 (Chen et al.) shows a ESD device comprised of a chain of parasitic BJTs.
U.S. Pat. No. 6,555,878B2 (Song et al.) shows a UMOS-like gate controlled Thyristor structure for ESD.
U.S. Pat. No. 6,611,028B2 (Cheng et al.) shows a substrate coupled ESD device.
U.S. Pat. No. 6,537,868b1 (Yu) shows a leakage current cascaded Diode structure.
U.S. Pat. No. 6,563,175B2 (Shiau et al.) shows a NMOS ESD device with silicide.
However, there is a need for an improved ESD devices and methods.